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Frequently Asked Questions (FAQ)
The LLVM Lexicon

Getting Started/Tutorials
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Reference
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User Guides
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- How To Build On ARM
- How To Build Clang and LLVM with Profile-Guided Optimizations
- How to cross-compile Clang/LLVM using Clang/LLVM
- LLVM Code Coverage Mapping Format
- Control Flow Verification Tool Design Document
- Building a Distribution of LLVM
- Building LLVM with CMake
- A guide to Dockerfiles for building LLVM
- Support Library
- Advanced Build Configurations
- Writing an LLVM Pass
- Writing an LLVM Pass (legacy PM version)
- LLVM’s Analysis and Transform Passes
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  - KernelInfo
  - Loop Fusion in LLVM
- Stack Safety Analysis
- MergeFunctions pass, how it works
- LLVM Alias Analysis Infrastructure
- MemorySSA
- MemProf: Memory Profiling for LLVM
- LLVM Loop Terminology (and Canonical Forms)
- LLVM Cycle Terminology
- Auto-Vectorization in LLVM
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  - Vectorization Plan
  - The Sandbox Vectorizer
- LLVM Link Time Optimization: Design and Implementation
- DTLTO
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- The LLVM gold plugin
- Remarks
- Source Level Debugging with LLVM
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  - Debug Info Assignment Tracking
- How to Update Debug Info: A Guide for LLVM Pass Authors
- The LLVM Instrumentor Pass
- Instruction referencing for debug info
- Debug info migration: From intrinsics to records
- Key Instructions debug info in LLVM and Clang
- Dynamic Debugging
- Future work
- Instrumentation Profile Format
- InstCombine contributor guide
- Writing an LLVM Backend
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  - How To Use Instruction Mappings
- The LLVM Target-Independent Code Generator
- TableGen Overview
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- MCJIT Design and Implementation
- ORC Design and Implementation
- JITLink and ORC’s ObjectLinkingLayer
- Debugging JIT-ed Code
- CommandLine 2.0 Library Manual
- Extending LLVM: Adding instructions, intrinsics, types, etc.
- How To Add A Constrained Floating-Point Intrinsic
- How to build Windows Itanium applications.
- How to Cross Compile Compiler-rt Builtins For Arm
- Using ARM NEON instructions in big-endian mode
- Support for AArch64 Scalable Matrix Extension in LLVM
- Compiling CUDA with clang
- User Guide for NVPTX Back-end
- User Guide for AMDGPU Backend
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- AMDGPU Asynchronous Operations
- AMDGPU DMA Operations
- AMDGPU Execution Synchronization
- AMDGPU Memory Model
- User Guide for SPIR-V Target
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- User Guide for the DirectX Target
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  - DirectX Container
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  - Architecture and Design of DXIL Support in LLVM
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  - Specification of DXIL Operations using TableGen Representation
  - DXIL Resource Handling
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  - Root Signatures
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  - Semantic Signatures
- User Guide for RISC-V Target
- RISC-V Vector Extension
- Scheduling Information for RISC-V VCIX Instructions
- Sandbox IR: A transactional layer over LLVM IR
- Telemetry framework in LLVM
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- Lightweight Fault Isolation (LFI) in LLVM
- LLVM Admin Tasks
- Benchmarking tips
- CMake Primer
- LLVM Community Code of Conduct
- FatLTO
- LLVM GitHub User Guide
- Markdown Quickstart Template
- Misexpect
- Opaque Pointers
- Using the New Pass Manager
- LLVM CoC Incident Reporting Guide
- Response Guide
- TableGen Fundamentals
- yaml2obj
Discourse Migration Guide

Getting Involved
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Request For Comment (RFC) process
Project Governance

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System Library#

Moved#

The System Library has been renamed to Support Library with documentation available at