Syntax of AMDGPU Instruction Operands#

Conventions#

The following notation is used throughout this document:

Notation

Description

{0..N}

Any integer value in the range from 0 to N (inclusive).

<x>

Syntax and meaning of x are explained elsewhere.

Notation	Description
{0..N}	Any integer value in the range from 0 to N (inclusive).
<x>	Syntax and meaning of x are explained elsewhere.

Operands#

v (32-bit)#

Vector registers. There are 256 32-bit vector registers.

A sequence of vector registers may be used to operate with more than 32 bits of data.

Assembler currently supports tuples with 1 to 12, 16 and 32 vector registers.

Syntax

Description

v<N>

A single 32-bit vector register.

N must be a decimal integer number.

v[<N>]

A single 32-bit vector register.

N may be specified as an integer number or an absolute expression.

v[<N>:<K>]

A sequence of (K-N+1) vector registers.

N and K may be specified as integer numbers or absolute expressions.

[v<N>, v<N+1>, … v<K>]

A sequence of (K-N+1) vector registers.

Register indices must be specified as decimal integer numbers.

Syntax	Description
v<N>	A single 32-bit vector register. N must be a decimal integer number.
v[<N>]	A single 32-bit vector register. N may be specified as an integer number or an absolute expression.
v[<N>:<K>]	A sequence of (K-N+1) vector registers. N and K may be specified as integer numbers or absolute expressions.
[v<N>, v<N+1>, … v<K>]	A sequence of (K-N+1) vector registers. Register indices must be specified as decimal integer numbers.

Note: N and K must satisfy the following conditions:

N <= K.
0 <= N <= 255.
0 <= K <= 255.
K-N+1 must be in the range from 1 to 12 or equal to 16 or 32.

GFX90A and GFX942 have an additional alignment requirement: pairs of vector registers must be even-aligned (first register must be even).

Examples:

v255
v[0]
v[0:1]
v[1:1]
v[0:3]
v[2*2]
v[1-1:2-1]
[v252]
[v252,v253,v254,v255]

Non-Sequential Address (NSA) Syntax

GFX10+ image instructions may use special NSA (Non-Sequential Address) syntax for image addresses:

Syntax

Description

[Vm, Vn, … Vk]

A sequence of 32-bit vector registers. Each register may be specified using the syntax defined above.

In contrast with the standard syntax, registers in NSA sequence are not required to have consecutive indices. Moreover, the same register may appear in the sequence more than once.

GFX11+ has an additional limitation: if address size occupies more than 5 dwords, registers starting from the 5th element must be contiguous.

Syntax	Description
[Vm, Vn, … Vk]	A sequence of 32-bit vector registers. Each register may be specified using the syntax defined above. In contrast with the standard syntax, registers in NSA sequence are not required to have consecutive indices. Moreover, the same register may appear in the sequence more than once. GFX11+ has an additional limitation: if address size occupies more than 5 dwords, registers starting from the 5th element must be contiguous.

Examples:

[v32,v1,v[2]]
[v[32],v[1:1],[v2]]
[v4,v4,v4,v4]

v (16-bit)#

16-bit vector registers. Each 32-bit vector register is divided into two 16-bit low and high registers, so there are 512 16-bit vector registers.

Only VOP3, VOP3P and VINTERP instructions may access all 512 registers (using op_sel modifier). VOP1, VOP2 and VOPC instructions may currently access only 128 low 16-bit registers using the syntax described below.

Warning

This section is incomplete. The support of 16-bit registers in the assembler is still WIP.

Syntax	Description
v<N>	A single 16-bit vector register (low half).

Note: N must satisfy the following conditions:

0 <= N <= 127.

Examples:

v127

a#

Accumulator registers. There are 256 32-bit accumulator registers.

A sequence of accumulator registers may be used to operate with more than 32 bits of data.

Assembler currently supports tuples with 1 to 12, 16 and 32 accumulator registers.

Syntax

Alternative Syntax (SP3)

Description

a<N>

acc<N>

A single 32-bit accumulator register.

N must be a decimal integer number.

a[<N>]

acc[<N>]

A single 32-bit accumulator register.

N may be specified as an integer number or an absolute expression.

a[<N>:<K>]

acc[<N>:<K>]

A sequence of (K-N+1) accumulator registers.

N and K may be specified as integer numbers or absolute expressions.

[a<N>, a<N+1>, … a<K>]

Syntax	Alternative Syntax (SP3)	Description
a<N>	acc<N>	A single 32-bit accumulator register. N must be a decimal integer number.
a[<N>]	acc[<N>]	A single 32-bit accumulator register. N may be specified as an integer number or an absolute expression.
a[<N>:<K>]	acc[<N>:<K>]	A sequence of (K-N+1) accumulator registers. N and K may be specified as integer numbers or absolute expressions.
[a<N>, a<N+1>, … a<K>]